That’s going to be a mass amount of porting. I’m not confident they can do it due to the difference in architecture and instruction sets. RISC V is a bit behind ARM for performance, and then to translate to Ryzen, I say that they are being too ambitious.
I know nothing about this, but I thought it should be easier since RISC-V has less instructions than x86-x64 and this would mostly result in lack of performance.
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That’s going to be a mass amount of porting. I’m not confident they can do it due to the difference in architecture and instruction sets. RISC V is a bit behind ARM for performance, and then to translate to Ryzen, I say that they are being too ambitious.
I know nothing about this, but I thought it should be easier since RISC-V has less instructions than x86-x64 and this would mostly result in lack of performance.